| ... | ... | @@ -16,8 +16,9 @@ The input file for the events on Intel® Haswell EP/EN/EX can be found [here] |
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- [Socket-wide counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#socket-wide-counters)
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- [Power counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#power-counters)
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- [Home Agent counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#home-agent-counters)
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- [LLC-to-QPI interface fixed-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#llc-to-qpi-interface-fixed-purpose-counters)
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- [LLC-to-QPI interface general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#llc-to-qpi-interface-general-purpose-counters)
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- [Ring-to-ring interface counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#ring-to-ring-interface-counters)
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- [QPI interface fixed-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#qpi-interface-fixed-purpose-counters)
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- [QPI interface general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#qpi-interface-general-purpose-counters)
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- [Last Level cache counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#last-level-cache-counters)
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- [Uncore management fixed-purpose counter](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#uncore-management-fixed-purpose-counter)
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- [Uncore management general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#uncore-management-general-purpose-counters)
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| ... | ... | @@ -731,7 +732,7 @@ The PCU performance counters are exposed to the operating system through the MSR |
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</TR>
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</TABLE>
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#### Memory controller fixed-purpose counter
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#### Memory controller fixed-purpose counters
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The Intel® Haswell EP/EN/EX microarchitecture provides measurements of the integrated Memory Controllers (iMC) in the uncore. The description from Intel®:<BR>
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<I>The Intel® Xeon processor E5 v3 family integrated Memory Controller provides the interface to DRAM and communicates to the rest of the uncore through the Home Agent (i.e. the IMC does not connect to the Ring).<BR>
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In conjunction with the HA, the memory controller also provides a variety of RAS features, such as ECC, lockstep, memory access retry, memory scrubbing, thermal throttling, mirroring, and rank sparing.
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| ... | ... | @@ -751,7 +752,7 @@ The integrated Memory Controllers performance counters are exposed to the operat |
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</TABLE>
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#### Memory controller general-purpose counter
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#### Memory controller general-purpose counters
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The Intel® Haswell EP/EN/EX microarchitecture provides measurements of the integrated Memory Controllers (iMC) in the uncore. The description from Intel®:<BR>
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<I>The Intel® Xeon processor E5 v3 family integrated Memory Controller provides the interface to DRAM and communicates to the rest of the uncore through the Home Agent (i.e. the IMC does not connect to the Ring).<BR>
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In conjunction with the HA, the memory controller also provides a variety of RAS features, such as ECC, lockstep, memory access retry, memory scrubbing, thermal throttling, mirroring, and rank sparing.
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| ... | ... | |
