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Updated architecture pages to have a link to the option descriptions authored by Thomas.Roehl's avatar Thomas.Roehl
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Ivy-Bridge-EP.md
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......@@ -60,13 +60,13 @@ Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose co
<TH>Comment</TH>
</TR>
<TR>
<TD>anythread</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#anythread">anythread</A></TD>
<TD>N</TD>
<TD>Set bit 2+(index*4) in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>kernel</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#kernel">kernel</A></TD>
<TD>N</TD>
<TD>Set bit (index*4) in config register</TD>
<TD></TD>
......@@ -107,31 +107,31 @@ The Intel&reg; IvyBridge microarchitecture provides 4 general-purpose counters c
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>kernel</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#kernel">kernel</A></TD>
<TD>N</TD>
<TD>Set bit 17 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>anythread</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#anythread">anythread</A></TD>
<TD>N</TD>
<TD>Set bit 21 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>invert</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
......@@ -147,13 +147,13 @@ The Intel&reg; IvyBridge EP/EN/EX microarchitecture provides measureing of offco
<TH>Comment</TH>
</TR>
<TR>
<TD>match0</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>16 bit hex value</TD>
<TD>Input value masked with 0x8FFF and written to bits 0-15 in the OFFCORE_RESPONSE register</TD>
<TD>Check the <A HREF="http://www.Intel&reg;.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel&reg; Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring</A> and <A HREF="https://download.01.org/perfmon/IVT">https://download.01.org/perfmon/IVT</A>.</TD>
</TR>
<TR>
<TD>match1</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>16 bit hex value</TD>
<TD>Input value is written to bits 16-37 in the OFFCORE_RESPONSE register</TD>
<TD>Check the <A HREF="http://www.Intel&reg;.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel&reg; Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring</A> and <A HREF="https://download.01.org/perfmon/IVT">https://download.01.org/perfmon/IVT</A>.</TD>
......@@ -238,31 +238,31 @@ The Home Agent performance counters are exposed to the operating system through
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>invert</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>opcode</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD>6 bit hex value</TD>
<TD>Set bits 0-5 in PCI_UNC_HA_PMON_OPCODEMATCH register of PCI device</TD>
<TD>A table of all valid opcodes can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
</TR>
<TR>
<TD>match0</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>46 bit hex address</TD>
<TD>Extract bits 6-31 and set bits 6-31 in PCI_UNC_HA_PMON_ADDRMATCH0 register of PCI device<BR>Extract bits 32-45 and set bits 0-13 in PCI_UNC_HA_PMON_ADDRMATCH1 register of PCI device</TD>
<TD></TD>
......@@ -324,43 +324,43 @@ The QPI hardware performance counters are exposed to the operating system throug
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>opcode</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD>6 bit hex value</TD>
<TD>Set bits 0-5 in PCI_UNC_HA_PMON_OPCODEMATCH register of PCI device</TD>
<TD></TD>
</TR>
<TR>
<TD>match0</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>32 bit hex address</TD>
<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_QPI_PMON_MATCH_0 register of PCI device</TD>
<TD>A description of matching capabilities can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
</TR>
<TR>
<TD>match1</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>20 bit hex address</TD>
<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_QPI_PMON_MATCH_1 register of PCI device</TD>
<TD>A description of matching capabilities can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
</TR>
<TR>
<TD>mask0</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
<TD>32 bit hex address</TD>
<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_QPI_PMON_MASK_0 register of PCI device</TD>
<TD>A description of masking capabilities can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
</TR>
<TR>
<TD>mask1</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
<TD>20 bit hex address</TD>
<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_QPI_PMON_MASK_1 register of PCI device</TD>
<TD>A description of masking capabilities can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
......@@ -405,43 +405,43 @@ The LLC hardware performance counters are exposed to the operating system throug
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 24-28 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>tid</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#tid">tid</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 0-4 in MSR_UNC_C&lt;0-15&gt;_PMON_BOX_FILTER register</TD>
<TD>A description of filter capabilities can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
</TR>
<TR>
<TD>state</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#state0xxxxx">state</A></TD>
<TD>6 bit hex value</TD>
<TD>Set bits 17-22 in MSR_UNC_C&lt;0-15&gt;_PMON_BOX_FILTER register</TD>
<TD>M: 0x28,<BR>F: 0x10,<BR>M: 0x08,<BR>E: 0x04,<BR>S: 0x02,<BR>I: 0x01</TD>
</TR>
<TR>
<TD>nid</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#nid">nid</A></TD>
<TD>16 bit hex value</TD>
<TD>Set bits 0-15 in MSR_UNC_C&lt;0-15&gt;_PMON_BOX_FILTER1 register</TD>
<TD>Note: Node 0 has value 0x0001</TD>
</TR>
<TR>
<TD>opcode</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD>9 bit hex value</TD>
<TD>Set bits 20-28 in MSR_UNC_C&lt;0-15&gt;_PMON_BOX_FILTER1 register</TD>
<TD>A table of all valid opcodes can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
</TR>
<TR>
<TD>match0</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>2 bit hex address</TD>
<TD>Set bits 30-31 in MSR_UNC_C&lt;0-15&gt;_PMON_BOX_FILTER1 register</TD>
<TD>A description of matching capabilities can be found in the <A HREF="http://www.Intel&reg;.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v2 uncore Manual</A>.</TD>
......@@ -504,13 +504,13 @@ The uncore management performance counters are exposed to the operating system t
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 24-28 in config register</TD>
<TD></TD>
......@@ -579,37 +579,37 @@ The power control unit offers four general-purpose counters. The PCU performance
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 24-28 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>match0</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>32 bit hex value</TD>
<TD>Set bits 0-31 in<BR>MSR_UNC_PCU_PMON_BOX_FILTER register</TD>
<TD>Band0: bits 0-7,<BR>Band1: bits 8-15,<BR>Band2: bits 16-23,<BR>Band3: bits 24-31</TD>
</TR>
<TR>
<TD>occupancy</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occupancy0xxxxx">occupancy</A></TD>
<TD>2 bit hex value</TD>
<TD>Set bit 14-15 in config register</TD>
<TD>Cores<BR>in C0: 0x1,<BR>in C3: 0x2,<BR>in C6: 0x3</TD>
</TR>
<TR>
<TD>occupancy_edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occ_edgedetect">occ_edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>occupancy_invert</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occ_invert">occ_invert</A></TD>
<TD>N</TD>
<TD>Set bit 30 in config register</TD>
<TD></TD>
......@@ -673,13 +673,13 @@ The memory controller counters are exposed to the operating system through PCI i
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......@@ -720,13 +720,13 @@ The R3QPI performance counters are exposed to the operating system through PCI i
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......@@ -771,13 +771,13 @@ The R2PCIe performance counters are exposed to the operating system through a PC
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......@@ -814,13 +814,13 @@ The IRP box counters are exposed to the operating system through the PCI interfa
<TH>Comment</TH>
</TR>
<TR>
<TD>edgedetect</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD>threshold</TD>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......