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Add invert option to most Uncore boxes. Was already implemented but not documented authored by Thomas.Roehl's avatar Thomas.Roehl
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Haswell-EP.md
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...@@ -421,6 +421,12 @@ The QPI hardware performance counters are exposed to the operating system throug ...@@ -421,6 +421,12 @@ The QPI hardware performance counters are exposed to the operating system throug
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD> <TD>8 bit hex value</TD>
...@@ -521,6 +527,12 @@ The LLC hardware performance counters are exposed to the operating system throug ...@@ -521,6 +527,12 @@ The LLC hardware performance counters are exposed to the operating system throug
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD> <TD>5 bit hex value</TD>
...@@ -582,13 +594,13 @@ The uncore management performance counters are exposed to the operating system t ...@@ -582,13 +594,13 @@ The uncore management performance counters are exposed to the operating system t
</TR> </TR>
<TR> <TR>
<TD>UBOXFIX</TD> <TD>UBOXFIX</TD>
<TD>UBOX_CLOCKTICKS</TD> <TD>UNCORE_CLOCK</TD>
</TR> </TR>
</TABLE> </TABLE>
### Uncore management general-purpose counters ### Uncore management general-purpose counters
The Intel&reg; Haswell EP/EN/EX microarchitecture provides measurements of the management box in the uncore. The description from Intel&reg;:<BR> The Intel&reg; Haswell EP/EN/EX microarchitecture provides measurements of the management box in the uncore. The description from Intel&reg;:<BR>
The UBox serves as the system configuration controller for the Intel Xeon processor E5 <I>The UBox serves as the system configuration controller for the Intel Xeon processor E5
v3 family. v3 family.
In this capacity, the UBox acts as the central unit for a variety of functions:</I> In this capacity, the UBox acts as the central unit for a variety of functions:</I>
- <I>The master for reading and writing physically distributed registers across Intel&reg; Xeon processor E5 v3 family using the Message Channel.</I> - <I>The master for reading and writing physically distributed registers across Intel&reg; Xeon processor E5 v3 family using the Message Channel.</I>
...@@ -625,6 +637,12 @@ The uncore management performance counters are exposed to the operating system t ...@@ -625,6 +637,12 @@ The uncore management performance counters are exposed to the operating system t
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD> <TD>5 bit hex value</TD>
...@@ -700,6 +718,12 @@ The PCU performance counters are exposed to the operating system through the MSR ...@@ -700,6 +718,12 @@ The PCU performance counters are exposed to the operating system through the MSR
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD> <TD>5 bit hex value</TD>
...@@ -797,6 +821,12 @@ The integrated Memory Controllers performance counters are exposed to the operat ...@@ -797,6 +821,12 @@ The integrated Memory Controllers performance counters are exposed to the operat
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD> <TD>8 bit hex value</TD>
...@@ -846,6 +876,12 @@ The Ring-to-QPI performance counters are exposed to the operating system through ...@@ -846,6 +876,12 @@ The Ring-to-QPI performance counters are exposed to the operating system through
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD> <TD>8 bit hex value</TD>
...@@ -898,6 +934,12 @@ The Ring-to-PCIe performance counters are exposed to the operating system throug ...@@ -898,6 +934,12 @@ The Ring-to-PCIe performance counters are exposed to the operating system throug
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD> <TD>8 bit hex value</TD>
...@@ -942,6 +984,12 @@ The IRP box counters are exposed to the operating system through the PCI interfa ...@@ -942,6 +984,12 @@ The IRP box counters are exposed to the operating system through the PCI interfa
<TD>Set bit 18 in config register</TD> <TD>Set bit 18 in config register</TD>
<TD></TD> <TD></TD>
</TR> </TR>
<TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR> <TR>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD> <TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD> <TD>8 bit hex value</TD>
... ...
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