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Add invert option to most Uncore boxes. Was already implemented but not documented
authored
May 17, 2016
by
Thomas.Roehl
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Haswell-EP.md
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@@ -421,6 +421,12 @@ The QPI hardware performance counters are exposed to the operating system throug
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
8 bit hex value
</TD>
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@@ -521,6 +527,12 @@ The LLC hardware performance counters are exposed to the operating system throug
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
5 bit hex value
</TD>
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@@ -582,13 +594,13 @@ The uncore management performance counters are exposed to the operating system t
</TR>
<TR>
<TD>
UBOXFIX
</TD>
<TD>
U
BOX
_CLOCK
TICKS
</TD>
<TD>
U
NCORE
_CLOCK
</TD>
</TR>
</TABLE>
### Uncore management general-purpose counters
The Intel
®
Haswell EP/EN/EX microarchitecture provides measurements of the management box in the uncore. The description from Intel
®
:
<BR>
The UBox serves as the system configuration controller for the Intel Xeon processor E5
<I>
The UBox serves as the system configuration controller for the Intel Xeon processor E5
v3 family.
In this capacity, the UBox acts as the central unit for a variety of functions:
</I>
-
<I>
The master for reading and writing physically distributed registers across Intel
®
Xeon processor E5 v3 family using the Message Channel.
</I>
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...
@@ -625,6 +637,12 @@ The uncore management performance counters are exposed to the operating system t
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
5 bit hex value
</TD>
...
...
@@ -700,6 +718,12 @@ The PCU performance counters are exposed to the operating system through the MSR
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
5 bit hex value
</TD>
...
...
@@ -797,6 +821,12 @@ The integrated Memory Controllers performance counters are exposed to the operat
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
8 bit hex value
</TD>
...
...
@@ -846,6 +876,12 @@ The Ring-to-QPI performance counters are exposed to the operating system through
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
8 bit hex value
</TD>
...
...
@@ -898,6 +934,12 @@ The Ring-to-PCIe performance counters are exposed to the operating system throug
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
8 bit hex value
</TD>
...
...
@@ -942,6 +984,12 @@ The IRP box counters are exposed to the operating system through the PCI interfa
<TD>
Set bit 18 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert"
>
invert
</A></TD>
<TD>
N
</TD>
<TD>
Set bit 23 in config register
</TD>
<TD></TD>
</TR>
<TR>
<TD><A
HREF=
"https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx"
>
threshold
</A></TD>
<TD>
8 bit hex value
</TD>
...
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...
