| ... | ... | @@ -62,13 +62,13 @@ Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose co |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>anythread</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#anythread">anythread</A></TD>
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<TD>N</TD>
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<TD>Set bit 2+(index*4) in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>kernel</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#kernel">kernel</A></TD>
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<TD>N</TD>
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<TD>Set bit (index*4) in config register</TD>
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<TD></TD>
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| ... | ... | @@ -110,43 +110,43 @@ The Intel® Haswell EP/EN/EX microarchitecture provides 4 general-purpose cou |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>kernel</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#kernel">kernel</A></TD>
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<TD>N</TD>
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<TD>Set bit 17 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>anythread</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#anythread">anythread</A></TD>
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<TD>N</TD>
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<TD>Set bit 21 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>8 bit hex value</TD>
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<TD>Set bits 24-31 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>invert</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
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<TD>N</TD>
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<TD>Set bit 23 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>in_transaction</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#in_transaction">in_transaction</A></TD>
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<TD>N</TD>
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<TD>Set bit 32 in config register</TD>
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<TD>Only available if Intel® Transactional Synchronization Extensions are available</TD>
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</TR>
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<TR>
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<TD>in_transaction_aborted</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#in_transaction_aborted">in_transaction_aborted</A></TD>
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<TD>N</TD>
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<TD>Set bit 33 in config register</TD>
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<TD>Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available</TD>
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| ... | ... | @@ -163,13 +163,13 @@ The Intel® Haswell EP/EN/EX microarchitecture provides measureing of offcore |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>match0</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
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<TD>16 bit hex value</TD>
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<TD>Input value masked with 0x8FFF and written to bits 0-15 in the OFFCORE_RESPONSE register</TD>
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<TD>Check the <A HREF="http://www.Intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring</A> and <A HREF="https://download.01.org/perfmon/SLM">https://download.01.org/perfmon/HSX</A>.</TD>
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</TR>
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<TR>
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<TD>match1</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
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<TD>22 bit hex value</TD>
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<TD>Input value is written to bits 16-37 in the OFFCORE_RESPONSE register</TD>
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<TD>Check the <A HREF="http://www.Intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring</A> and <A HREF="https://download.01.org/perfmon/SLM">https://download.01.org/perfmon/HSX</A>.</TD>
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| ... | ... | @@ -257,31 +257,31 @@ The Home Agent performance counters are exposed to the operating system through |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>8 bit hex value</TD>
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<TD>Set bits 24-31 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>invert</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
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<TD>N</TD>
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<TD>Set bit 23 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>opcode</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
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<TD>6 bit hex value</TD>
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<TD>Set bits 0-5 in PCI_UNC_HA_PMON_OPCODEMATCH register of PCI device</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>match0</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
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<TD>46 bit hex address</TD>
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<TD>Extract bits 6-31 and set bits 6-31 in PCI_UNC_HA_PMON_ADDRMATCH0 register of PCI device<BR>Extract bits 32-45 and set bits 0-13 in PCI_UNC_HA_PMON_ADDRMATCH1 register of PCI device</TD>
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<TD></TD>
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| ... | ... | @@ -327,25 +327,25 @@ The SBOX hardware performance counters are exposed to the operating system throu |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>8 bit hex value</TD>
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<TD>Set bits 24-31 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>invert</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
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<TD>N</TD>
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<TD>Set bit 23 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>tid</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#tid">tid</A></TD>
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<TD>N</TD>
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<TD>Set bit 19 in config register</TD>
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<TD>This option has no real effect because TID filtering can be activated but there is no possibility to specify the TID somewhere.</TD>
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| ... | ... | @@ -415,61 +415,61 @@ The QPI hardware performance counters are exposed to the operating system throug |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>8 bit hex value</TD>
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<TD>Set bits 24-31 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>match0</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
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<TD>32 bit hex address</TD>
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<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_RX_MATCH_0 register of PCI device</TD>
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<TD>This option matches the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>match1</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
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<TD>20 bit hex address</TD>
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<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_RX_MATCH_1 register of PCI device</TD>
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<TD>This option matches the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>match2</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match2</A></TD>
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<TD>32 bit hex address</TD>
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<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_TX_MATCH_0 register of PCI device</TD>
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<TD>This option matches the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>match3</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match3</A></TD>
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<TD>20 bit hex address</TD>
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<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_TX_MATCH_1 register of PCI device</TD>
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<TD>This option matches the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>mask0</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
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<TD>32 bit hex address</TD>
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<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_RX_MASK_0 register of PCI device</TD>
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<TD>This option masks the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>mask1</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
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<TD>20 bit hex address</TD>
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<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_RX_MASK_1 register of PCI device</TD>
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<TD>This option masks the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>mask2</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask2</A></TD>
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<TD>32 bit hex address</TD>
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<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_TX_MASK_0 register of PCI device</TD>
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<TD>This option masks the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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</TR>
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<TR>
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<TD>mask3</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask3</A></TD>
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<TD>20 bit hex address</TD>
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<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_TX_MASK_1 register of PCI device</TD>
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<TD>This option masks the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
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| ... | ... | @@ -515,43 +515,43 @@ The LLC hardware performance counters are exposed to the operating system throug |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>5 bit hex value</TD>
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<TD>Set bits 24-28 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>tid</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#tid">tid</A></TD>
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<TD>5 bit hex value</TD>
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<TD>Set bits 0-4 in MSR_UNC_C<0-17>_PMON_BOX_FILTER register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>state</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#state0xxxxx">state</A></TD>
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<TD>6 bit hex value</TD>
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<TD>Set bits 17-22 in MSR_UNC_C<0-17>_PMON_BOX_FILTER register</TD>
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<TD>M: 0x28,<BR>F: 0x10,<BR>M: 0x08,<BR>E: 0x04,<BR>S: 0x02,<BR>I: 0x01</TD>
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</TR>
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<TR>
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<TD>nid</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#nid">nid</A></TD>
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<TD>16 bit hex value</TD>
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<TD>Set bits 0-15 in MSR_UNC_C<0-17>_PMON_BOX_FILTER1 register</TD>
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<TD>Note: Node 0 has value 0x0001</TD>
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</TR>
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<TR>
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<TD>opcode</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
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<TD>9 bit hex value</TD>
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<TD>Set bits 20-28 in MSR_UNC_C<0-17>_PMON_BOX_FILTER1 register</TD>
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<TD>A list of valid opcodes can be found in the <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A>.</TD>
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</TR>
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<TR>
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<TD>match0</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
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<TD>2 bit hex address</TD>
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<TD>Set bits 30-31 in MSR_UNC_C<0-17>_PMON_BOX_FILTER1 register</TD>
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<TD>See the <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel® Xeon E5-2600 v3 uncore Manual</A> for more information.</TD>
|
| ... | ... | @@ -619,13 +619,13 @@ The uncore management performance counters are exposed to the operating system t |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>5 bit hex value</TD>
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<TD>Set bits 24-28 in config register</TD>
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<TD></TD>
|
| ... | ... | @@ -694,37 +694,37 @@ The PCU performance counters are exposed to the operating system through the MSR |
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<TH>Comment</TH>
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</TR>
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<TR>
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<TD>edgedetect</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
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<TD>N</TD>
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<TD>Set bit 18 in config register</TD>
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<TD></TD>
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</TR>
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<TR>
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<TD>threshold</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
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<TD>5 bit hex value</TD>
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<TD>Set bits 24-28 in config register</TD>
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<TD></TD>
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</TR>
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|
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<TR>
|
|
|
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<TD>match0</TD>
|
|
|
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
|
|
|
|
<TD>32 bit hex value</TD>
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|
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<TD>Set bits 0-31 in<BR>MSR_UNC_PCU_PMON_BOX_FILTER register</TD>
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<TD>Band0: bits 0-7,<BR>Band1: bits 8-15,<BR>Band2: bits 16-23,<BR>Band3: bits 24-31</TD>
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</TR>
|
|
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<TR>
|
|
|
|
<TD>occupancy</TD>
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<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occupancy0xxxxx">occupancy</A></TD>
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|
|
|
<TD>2 bit hex value</TD>
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|
|
|
<TD>Set bit 14-15 in config register</TD>
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|
|
|
<TD>Cores<BR>in C0: 0x1,<BR>in C3: 0x2,<BR>in C6: 0x3</TD>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>occupancy_edgedetect</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occ_edgedetect">occ_edgedetect</A></TD>
|
|
|
|
<TD>N</TD>
|
|
|
|
<TD>Set bit 31 in config register</TD>
|
|
|
|
<TD></TD>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>occupancy_invert</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occ_invert">occ_invert</A></TD>
|
|
|
|
<TD>N</TD>
|
|
|
|
<TD>Set bit 30 in config register</TD>
|
|
|
|
<TD></TD>
|
| ... | ... | @@ -791,13 +791,13 @@ The integrated Memory Controllers performance counters are exposed to the operat |
|
|
|
<TH>Comment</TH>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>edgedetect</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
|
|
|
|
<TD>N</TD>
|
|
|
|
<TD>Set bit 18 in config register</TD>
|
|
|
|
<TD></TD>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>threshold</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
|
|
|
|
<TD>8 bit hex value</TD>
|
|
|
|
<TD>Set bits 24-31 in config register</TD>
|
|
|
|
<TD></TD>
|
| ... | ... | @@ -840,13 +840,13 @@ The Ring-to-QPI performance counters are exposed to the operating system through |
|
|
|
<TH>Comment</TH>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>edgedetect</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
|
|
|
|
<TD>N</TD>
|
|
|
|
<TD>Set bit 18 in config register</TD>
|
|
|
|
<TD></TD>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>threshold</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
|
|
|
|
<TD>8 bit hex value</TD>
|
|
|
|
<TD>Set bits 24-31 in config register</TD>
|
|
|
|
<TD></TD>
|
| ... | ... | @@ -892,13 +892,13 @@ The Ring-to-PCIe performance counters are exposed to the operating system throug |
|
|
|
<TH>Comment</TH>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>edgedetect</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
|
|
|
|
<TD>N</TD>
|
|
|
|
<TD>Set bit 18 in config register</TD>
|
|
|
|
<TD></TD>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>threshold</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
|
|
|
|
<TD>8 bit hex value</TD>
|
|
|
|
<TD>Set bits 24-31 in config register</TD>
|
|
|
|
<TD></TD>
|
| ... | ... | @@ -936,13 +936,13 @@ The IRP box counters are exposed to the operating system through the PCI interfa |
|
|
|
<TH>Comment</TH>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>edgedetect</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
|
|
|
|
<TD>N</TD>
|
|
|
|
<TD>Set bit 18 in config register</TD>
|
|
|
|
<TD></TD>
|
|
|
|
</TR>
|
|
|
|
<TR>
|
|
|
|
<TD>threshold</TD>
|
|
|
|
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
|
|
|
|
<TD>8 bit hex value</TD>
|
|
|
|
<TD>Set bits 24-31 in config register</TD>
|
|
|
|
<TD></TD>
|
| ... | ... | |
