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Haswell-EP.md
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## Performance groups
[Intel® Haswell EP/EN/EX Performance groups](https://github.com/rrze-likwid/likwid/tree/master/groups/haswellEP)
[Intel® Haswell EP/EN/EX Performance groups](https://github.com/RRZE-HPC/likwid/tree/master/groups/haswellEP)
## Events
The input file for the events on Intel® Haswell EP/EN/EX can be found [here](https://github.com/rrze-likwid/likwid/blob/master/src/includes/perfmon_haswellEP_events.txt).
The input file for the events on Intel® Haswell EP/EN/EX can be found [here](https://github.com/RRZE-HPC/likwid/blob/master/src/includes/perfmon_haswellEP_events.txt).
## Counters
- [Core-local counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#core-local-counters)
- [Fixed-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#fixed-purpose-counters)
- [General-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#general-purpose-counters)
- [Thermal counter](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#thermal-counter)
- [Socket-wide counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#socket-wide-counters)
- [Energy counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#energy-counters)
- [Home Agent counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#home-agent-counters)
- [Ring-to-ring interface counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#ring-to-ring-interface-counters)
- [QPI interface fixed-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#qpi-interface-fixed-purpose-counters)
- [QPI interface general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#qpi-interface-general-purpose-counters)
- [Last Level cache counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#last-level-cache-counters)
- [Uncore management fixed-purpose counter](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#uncore-management-fixed-purpose-counter)
- [Uncore management general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#uncore-management-general-purpose-counters)
- [Power control unit fixed-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#power-control-unit-fixed-purpose-counters)
- [Power control unit general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#power-control-unit-general-purpose-counters)
- [Memory controller fixed-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#memory-controller-fixed-purpose-counters)
- [Memory controller general-purpose counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#memory-controller-general-purpose-counters)
- [Ring-to-QPI counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#ring-to-qpi-counters)
- [Ring-to-PCIe counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#ring-to-pcie-counters)
- [IRP box counters](https://github.com/rrze-likwid/likwid/wiki/Haswell-EP#irp-box-counters)
- [Core-local counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#core-local-counters)
- [Fixed-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#fixed-purpose-counters)
- [General-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#general-purpose-counters)
- [Thermal counter](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#thermal-counter)
- [Socket-wide counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#socket-wide-counters)
- [Energy counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#energy-counters)
- [Home Agent counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#home-agent-counters)
- [Ring-to-ring interface counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#ring-to-ring-interface-counters)
- [QPI interface fixed-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#qpi-interface-fixed-purpose-counters)
- [QPI interface general-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#qpi-interface-general-purpose-counters)
- [Last Level cache counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#last-level-cache-counters)
- [Uncore management fixed-purpose counter](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#uncore-management-fixed-purpose-counter)
- [Uncore management general-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#uncore-management-general-purpose-counters)
- [Power control unit fixed-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#power-control-unit-fixed-purpose-counters)
- [Power control unit general-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#power-control-unit-general-purpose-counters)
- [Memory controller fixed-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#memory-controller-fixed-purpose-counters)
- [Memory controller general-purpose counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#memory-controller-general-purpose-counters)
- [Ring-to-QPI counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#ring-to-qpi-counters)
- [Ring-to-PCIe counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#ring-to-pcie-counters)
- [IRP box counters](https://github.com/RRZE-HPC/likwid/wiki/Haswell-EP#irp-box-counters)
### Core-local counters
......@@ -63,13 +63,13 @@ Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose co
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#anythread">anythread</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#anythread">anythread</A></TD>
<TD>N</TD>
<TD>Set bit 2+(index*4) in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#kernel">kernel</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#kernel">kernel</A></TD>
<TD>N</TD>
<TD>Set bit (index*4) in config register</TD>
<TD></TD>
......@@ -111,43 +111,43 @@ The Intel&reg; Haswell EP/EN/EX microarchitecture provides 4 general-purpose cou
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#kernel">kernel</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#kernel">kernel</A></TD>
<TD>N</TD>
<TD>Set bit 17 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#anythread">anythread</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#anythread">anythread</A></TD>
<TD>N</TD>
<TD>Set bit 21 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#in_transaction">in_transaction</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#in_transaction">in_transaction</A></TD>
<TD>N</TD>
<TD>Set bit 32 in config register</TD>
<TD>Only available if Intel&reg; Transactional Synchronization Extensions are available</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#in_transaction_aborted">in_transaction_aborted</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#in_transaction_aborted">in_transaction_aborted</A></TD>
<TD>N</TD>
<TD>Set bit 33 in config register</TD>
<TD>Only counter PMC2 and only if Intel&reg; Transactional Synchronization Extensions are available</TD>
......@@ -164,13 +164,13 @@ The Intel&reg; Haswell EP/EN/EX microarchitecture provides measureing of offcore
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>16 bit hex value</TD>
<TD>Input value masked with 0x8FFF and written to bits 0-15 in the OFFCORE_RESPONSE register</TD>
<TD>Check the <A HREF="http://www.Intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel&reg; Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring</A> and <A HREF="https://download.01.org/perfmon/SLM">https://download.01.org/perfmon/HSX</A>.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>22 bit hex value</TD>
<TD>Input value is written to bits 16-37 in the OFFCORE_RESPONSE register</TD>
<TD>Check the <A HREF="http://www.Intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html">Intel&reg; Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring</A> and <A HREF="https://download.01.org/perfmon/SLM">https://download.01.org/perfmon/HSX</A>.</TD>
......@@ -258,31 +258,31 @@ The Home Agent performance counters are exposed to the operating system through
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD>6 bit hex value</TD>
<TD>Set bits 0-5 in PCI_UNC_HA_PMON_OPCODEMATCH register of PCI device</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>46 bit hex address</TD>
<TD>Extract bits 6-31 and set bits 6-31 in PCI_UNC_HA_PMON_ADDRMATCH0 register of PCI device<BR>Extract bits 32-45 and set bits 0-13 in PCI_UNC_HA_PMON_ADDRMATCH1 register of PCI device</TD>
<TD></TD>
......@@ -328,25 +328,25 @@ The SBOX hardware performance counters are exposed to the operating system throu
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#invert">invert</A></TD>
<TD>N</TD>
<TD>Set bit 23 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#tid0xxxxx">tid</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#tid0xxxxx">tid</A></TD>
<TD>N</TD>
<TD>Set bit 19 in config register</TD>
<TD>This option has no real effect because TID filtering can be activated but there is no possibility to specify the TID somewhere.</TD>
......@@ -416,61 +416,61 @@ The QPI hardware performance counters are exposed to the operating system throug
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>32 bit hex address</TD>
<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_RX_MATCH_0 register of PCI device</TD>
<TD>This option matches the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>20 bit hex address</TD>
<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_RX_MATCH_1 register of PCI device</TD>
<TD>This option matches the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match2</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match2</A></TD>
<TD>32 bit hex address</TD>
<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_TX_MATCH_0 register of PCI device</TD>
<TD>This option matches the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match3</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match3</A></TD>
<TD>20 bit hex address</TD>
<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_TX_MATCH_1 register of PCI device</TD>
<TD>This option matches the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
<TD>32 bit hex address</TD>
<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_RX_MASK_0 register of PCI device</TD>
<TD>This option masks the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#mask0-30xxxxx">mask0</A></TD>
<TD>20 bit hex address</TD>
<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_RX_MASK_1 register of PCI device</TD>
<TD>This option masks the receive side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask2</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#mask0-30xxxxx">mask2</A></TD>
<TD>32 bit hex address</TD>
<TD>Input value masked with 0x8003FFF8 and written to bits 0-31 in the PCI_UNC_V3_QPI_PMON_TX_MASK_0 register of PCI device</TD>
<TD>This option masks the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#mask0-30xxxxx">mask3</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#mask0-30xxxxx">mask3</A></TD>
<TD>20 bit hex address</TD>
<TD>Input value masked with 0x000F000F and written to bits 0-19 in the PCI_UNC_V3_QPI_PMON_TX_MASK_1 register of PCI device</TD>
<TD>This option masks the transmit side. Check <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for bit fields.</TD>
......@@ -516,43 +516,43 @@ The LLC hardware performance counters are exposed to the operating system throug
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 24-28 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#tid0xxxxx">tid</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#tid0xxxxx">tid</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 0-4 in MSR_UNC_C&lt;0-17&gt;_PMON_BOX_FILTER register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#state0xxxxx">state</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#state0xxxxx">state</A></TD>
<TD>6 bit hex value</TD>
<TD>Set bits 17-22 in MSR_UNC_C&lt;0-17&gt;_PMON_BOX_FILTER register</TD>
<TD>M: 0x28,<BR>F: 0x10,<BR>M: 0x08,<BR>E: 0x04,<BR>S: 0x02,<BR>I: 0x01</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#nid0xxxxx">nid</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#nid0xxxxx">nid</A></TD>
<TD>16 bit hex value</TD>
<TD>Set bits 0-15 in MSR_UNC_C&lt;0-17&gt;_PMON_BOX_FILTER1 register</TD>
<TD>Note: Node 0 has value 0x0001</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#opcode0xxxxx">opcode</A></TD>
<TD>9 bit hex value</TD>
<TD>Set bits 20-28 in MSR_UNC_C&lt;0-17&gt;_PMON_BOX_FILTER1 register</TD>
<TD>A list of valid opcodes can be found in the <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A>.</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>2 bit hex address</TD>
<TD>Set bits 30-31 in MSR_UNC_C&lt;0-17&gt;_PMON_BOX_FILTER1 register</TD>
<TD>See the <A HREF="http://www.Intel.de/content/www/de/de/processors/xeon/xeon-e5-2600-v2-uncore-manual.html">Intel&reg; Xeon E5-2600 v3 uncore Manual</A> for more information.</TD>
......@@ -620,13 +620,13 @@ The uncore management performance counters are exposed to the operating system t
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 24-28 in config register</TD>
<TD></TD>
......@@ -695,37 +695,37 @@ The PCU performance counters are exposed to the operating system through the MSR
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>5 bit hex value</TD>
<TD>Set bits 24-28 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#match0-30xxxxx">match0</A></TD>
<TD>32 bit hex value</TD>
<TD>Set bits 0-31 in<BR>MSR_UNC_PCU_PMON_BOX_FILTER register</TD>
<TD>Band0: bits 0-7,<BR>Band1: bits 8-15,<BR>Band2: bits 16-23,<BR>Band3: bits 24-31</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occupancy0xxxxx">occupancy</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#occupancy0xxxxx">occupancy</A></TD>
<TD>2 bit hex value</TD>
<TD>Set bit 14-15 in config register</TD>
<TD>Cores<BR>in C0: 0x1,<BR>in C3: 0x2,<BR>in C6: 0x3</TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occ_edgedetect">occ_edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#occ_edgedetect">occ_edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 31 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#occ_invert">occ_invert</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#occ_invert">occ_invert</A></TD>
<TD>N</TD>
<TD>Set bit 30 in config register</TD>
<TD></TD>
......@@ -792,13 +792,13 @@ The integrated Memory Controllers performance counters are exposed to the operat
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......@@ -841,13 +841,13 @@ The Ring-to-QPI performance counters are exposed to the operating system through
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......@@ -893,13 +893,13 @@ The Ring-to-PCIe performance counters are exposed to the operating system throug
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
......@@ -937,13 +937,13 @@ The IRP box counters are exposed to the operating system through the PCI interfa
<TH>Comment</TH>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#edgedetect">edgedetect</A></TD>
<TD>N</TD>
<TD>Set bit 18 in config register</TD>
<TD></TD>
</TR>
<TR>
<TD><A HREF="https://github.com/rrze-likwid/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD><A HREF="https://github.com/RRZE-HPC/likwid/wiki/DescOptions#threshold0xxxxx">threshold</A></TD>
<TD>8 bit hex value</TD>
<TD>Set bits 24-31 in config register</TD>
<TD></TD>
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